A major goal in the fabrication of integrated circuitry is reduction of the surface area utilized to fabricate various devices. One structure which occupies a great deal of surface area is the isolation structure. A common requirement in nearly all integrated circuitry is that isolation structures must be provided between elements formed in the surface of the integrated circuit. Isolation structures attempt to provide electrical isolation between components so that, as much as possible, each element may operate independently of other elements outside of the direct and intentional interconnection of various circuit elements.
The most common method of isolation employed today is the use of field oxidation. In this structure, regions between elements are implanted with a channel stop implant and then a thick field oxide region is formed, usually by thermal growth, to form the field isolation structure. This structure provides electrically insulating oxide and a depletion region between elements in the integrated circuit. This method suffers from two major drawbacks. First, because the field oxide region must be patterned of the surface of the substrate, the field isolation structure must occupy an area at least equal to the minimum geometry provided by the lithography system used to pattern the field oxide mask. In addition, when field oxide regions are thermally grown, as is usually the case, the field oxide region expands laterally as well as vertically, thus occupying an even greater surface area. Also, the field oxide structure does not completely enclose the region containing the active element thereby leaving a direct, although extended, connection between regions containing active elements. A particularly problematic situation caused by the second problem involves the problem of latch-up in CMOS circuitry. Latch-up occurs when an injection of spurious minority carriers causes the thyristor formed by the P-type source of the P-channel MOS transistor, which is usually connected to the positive supply voltage, the N-type tank of the P-channel transistor, the P-type well containing the N-channel transistor and the N-type source of the N-channel transistor which is usually connected to ground potential, to turn on. Thus a large current flows from positive voltage supply to ground, usually destroying the latched-up devices. Several structures have been developed to minimize the potential for latch-up; however, these stuctures require at least a 4 micron space between devices.